Integrated Circuit Defect Diagnosis using Machine Learning
Our patent has now officially been granted.
Blog
News, reviews of my and others’ published work, critique of interesting technical content, and more.
2025
2022
Machine Learning in Logic Circuit Diagnosis
Our book’s finally going to be published in Feb 2023! Pre-order it now from Amazon or Barnes & Noble. It showcases the use of different machine learning ...
Industry Evaluation of Reversible Scan Chain Diagnosis
I presented this paper at the International Test Conference (ITC), 2022.
2021
Improving Diagnosis Resolution with Population Level Statistical Diagnosis
This paper was presented at the International Symposium for Testing and Failure Analysis (ISTFA), 2021.
Integrated Circuit Defect Diagnosis Using Machine Learning
Our patent (16/986,963) filing is published now.
2020
Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer
This work is published in the ACM Transactions on Design Automation of Electronic Systems (TODAES), 2020.
A Deterministic-Statistical Multiple-Defect Diagnosis Methodology
I presented this paper at the VLSI Test Symposium (VTS), 2020.
Learning Enhanced Diagnosis of Logic Circuit Failures
Orally defended my PhD thesis today!
2019
PhD Forum Competition
I won the 2019 PhD Forum Contest, which was held at the IEEE European Test Symposium (ETS), Baden-Baden, Germany. The goal of the competition is to provide a...
LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis Methodology
I presented this paper at the European Test Symposium (ETS), 2019.
Doctoral Thesis Award
I participated in the 2019 TTTC’s E.J. McCluskey Best Doctoral Thesis Award, which was held at the IEEE VLSI Test Symposium (VTS), Monterey, CA, USA. The pur...
Diagnosis Outcome Preview through Learning
This work was presented at the VLSI Test Symposium (VTS), 2019.
An Automated Methodology for Logic Characterization Vehicle Design
This paper is published in the Electronic Design Failure Analysis (EDFA) Magazine, ASM International, Feb 2019
2018
Improving Diagnosis Efficiency via Machine Learning
This work was presented at the International Test Conference (ITC), 2018.
NOIDA: Noise-resistant Intra-cell Diagnosis
I presented this paper at the VLSI Test Symposium (VTS), 2018.
2017
Neil and Jo Bushnell Fellowship in Engineering
I was selected (out of >800 students) to receive the prestigious 2017 Neil and Jo Bushnell Fellowship in Engineering by Carnegie Institute of Technology, ...
PADLOC: Physically-Aware Defect Localization and Characterization
I presented this paper at the Asian Test Symposium (ATS), 2017.
Multiple-defect Diagnosis for Logic Characterization Vehicles
This paper was presented at the European Test Symposium (ETS), 2017.
2016
Test Chip Design for Optimal Cell-aware Diagnosability
I presented this paper at the International Test Conference (ITC), 2016.
Logic Characterization Vehicle Design Reflection via Layout Rewiring
This paper was presented at the International Test Conference (ITC), 2016.
Logic Characterization Vehicle Design for Yield Learning
This paper was presented at the Advanced Semiconductor Manufacturing Conference (ASMC), 2016.
Achieving 100% Cell-aware Coverage by Design
This paper was presented at the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016.